My presumption is that the Xeon side is only leverage 1 DPC either with different system board or a dual socket 2 DPC configuration to get to 128 DIMMs in total.

Other alternative is that since this is a SAP HANA appliance, it simply has an artificial limit of 16 TB regardless of hardware.

AMD explains it (though not for x86, but equally applicable) thusly:

“When the ECC mode is enabled, a write operation computes and stores an ECC code along with the data, and a read operation reads and checks the data against the stored ECC code. Consequently, it is possible to receive ECC errors when reading uninitialized memory locations. To avoid this problem, *** all memory locations must be written before being read ***. Writing to the entire DDR DRAM through the CPU can be time intensive. It might be worthwhile to use a DMA device to generate larger bursts to the DDR controller initialization and offload the CPU.”.

I’m not aware of DMA being used to initialize DRAM and 16TBs would take over an hour, don’t know why (with a new memory controller) this problem wouldn’t be resolved with DDR5 but I also don’t know that it is.

In addition server motherboards take a very long time to boot with very little memory, don’t know how they get their 9’s without failover to hide boot times.

One (other) benefit of CXL is that the large single pool of memory can be divided between the processors dynamically, to avoid overprovisioning; don’t know that is happening here (or in the prior system reviewed here), but if it’s not then it’s simply the ability to add additional memory beyond what would fit on the slots on the motherboard.