Comments on: ASUS AMD EPYC CXL Memory Enabled Server AI and More OCP Summit 2024

By: Mark Hahn

Mark Hahn — Sun, 10 Nov 2024 16:27:11 +0000

Hard to imagine telling us any less about the cxl! What’s the topology? Can the cxl RAM be used by any of the 4 nodes, and how do they arbitrate? What’s the bandwidth and latency?

By: michaelp

michaelp — Fri, 01 Nov 2024 18:03:09 +0000

Page 1 “The 2.5″ bays take up a lot of the rear panel”
I think you mean “The 2.5″ bays take up a lot of the **front** panel”

By: emerth

emerth — Fri, 01 Nov 2024 12:53:14 +0000

Oh, nevermind. Trick of perspective, the big black heatsink looks like it would block any more slots.

By: emerth

emerth — Fri, 01 Nov 2024 12:49:22 +0000

It is not obvious where the other four GPUs fit into the ASUS ESC8000A E13P. Is it a two level system with another four down below, or is ASUS shining us a bit with an eight-slot single slot spacing board and calling that eight GPUs?

By: fuzzyfuzzyfungus

fuzzyfuzzyfungus — Fri, 01 Nov 2024 12:23:25 +0000

On the CXL system; is there any sort of inter-node connection to allow flexible allocation of the additional RAM; or is it purely a measure to allow more DIMMs than the width limits of a 2U4N and the trace length limits of the primary memory buss would ordinarily permit?

I’d assume that the latter is vastly simpler and more widely compatible; but a lot of the CXL announcements one sees emphasize the potential of some degree of disaggregation/flexible allocation of RAM to nodes; and it is presumably easier to get 4 of your own motherboards talking to one another than it is to be ready for some sort of SAN-for-RAM style thing with mature multi-vendor interoperability and established standards for administration.