Plus, it looks nicer and more symmetrical and I like a symmetrical looking board layout. :-)

Yes, that’s true. But the layout I’m suggesting would allow for future processors that support 16 or possibly even 20 channels of memory. They’d still be able to do only 12 channels per CPU with my revised layout. They’d just have a good bit of extra space along the left and right edges for all those VRMs and glue logic chips. And when they get to 16-channel memory I/O, those VRMs and glue logics can be re-arranged to the top and bottom edges of the CPU and DIMM blocks, with room left over for all the MCIO and NVMe connectors for everything else. They’re already using an 18-inch wide proprietary board anyway, might as well use that space. Either way, the internal volume of server frames is going to have to increase unless the engineers make the decision to use multi-channel RAM modules with local memory controllers on them as has been done before in some of IBM’s mainframes and POWER architecture servers.

Yabbut, 6 or 8 more would be weird when you have 12 memory channels. Also you need to consider the strain on the memory controller.