Comments on: ASRock Rack SIENAD8-2L2T AMD EPYC 8004 Siena Motherboard Review

By: Rick

Rick — Sat, 18 Jan 2025 12:32:31 +0000

I’m planning to just plant 3 PCIe to 2x MCIO8i onto the board, use two of those for NVMe storage, and the third with two MCIO to SATA adapters.
Since it’s a dumb adapter, and each data lane is just signalling SATA instead of PCIe, I would expect this to be the most flexible breakout, as it would allow me to switch to additional NVMe in the future, with the highest likelihood of still getting at least reliable PCIe4 off those lanes.
Would appreciate if anyone else managed to get SATA off this board, as decent 16x HBAs are going to inflict even more damage to an already well over-budget build.

Also, does anyone know if this supports PCIe hotplugging? With MCIO and nvme backplanes, this should be a common feature by now, but documentation is non-existant.

By: Majlou

Majlou — Wed, 24 Jul 2024 13:37:54 +0000

“It is a small touch but it would save a few seconds per installation.”

Please! No manufacturers custom tool-less mounting mechanism. The M.2 drive cooler incompatibility is not worth a few seconds per installation.

By: Brandon P

Brandon P — Thu, 30 May 2024 18:17:03 +0000

Does anyone know when this will actually be readily available? I’d love to build a server with this mobo and the 8224p.

By: emerth

emerth — Thu, 28 Mar 2024 17:03:48 +0000

@Mike, @Mama, @ajr – thanks for the breakout board info. I did look for something like that on asrockrack site but I had no luck.

By: Kevin G

Kevin G — Thu, 28 Mar 2024 15:37:53 +0000

Admittedly an edge case here, but has a Threadripper or Threadripper Pro CPU been dropped into this board? I am curious what the unofficial interoperability is with Siena and AMD’s workstation parts on a board like this is. (Of course the official support is no but has anyone tried it?) I want to know mainly because AMD is doing some interesting segmentation between these platforms like Siena leveraging Zen4c chiplets for increased density/lower power while Threadrippers use the vanilla Zen 4 chiplets for higher clocks. I suspect that with Zen 5 and Zen 6 on the horizon, AMD will be distinguishing these platforms with differences in V-cache and accelerators.

By: Kyle

Kyle — Thu, 28 Mar 2024 15:36:04 +0000

@Eric
In the default configuration the allocator has no knowledge of the memory topology, it has a map of valid physical memory addresses and that’s it. It’s the job of memory controllers in the CPU to manage optimal placement.
Software control is possible only with NUMA, and even then it heavily depends on the implementation.
I’d imagine the two dual-DIMM channels are there for use cases requiring more RAM for the price of slight bandwidth reduction (when compared to more single-DIMM channels). Probably ASRockRack had place near the socket to spare, so why not. I’ve seen Intel Supermicro boards doing the same thing.