Comments on: Why 2 DIMMs Per Channel Will Matter Less in Servers

By: Rob

Rob — Sun, 18 Feb 2024 09:42:59 +0000

Just wait for SP7 and its 16 channels, that will take up a lot of space.

Maybe angling the sockets to 30° and splitting them between both sides of the motherboard will be the solution. That’s probably better than rotating both the CPU and memory sockets 90° and implementing ‘cross flow’ cooling.

By: Kamen Rider Blade

Kamen Rider Blade — Thu, 20 Apr 2023 00:53:10 +0000

IBM was also correct in that OMI (Open Memory Interface) was the solution.
The dumb part was that they wanted to move the Memory Controller onto the DIMM.

That’s a big “No No” for DIMM costs. That’s the Bridge too far, or flying too close to the sun and having your wings melt off.

The OMI model that should be adopted is the one where the Memory Controller is soldered onto the Server MoBo, near the DIMM slots.

Small Chiplet based Memory Controllers with a extra short trace connection length between the Memory Controller and the Parallel connections on the DIMM would help increase and stabilize future higher speed Memory w/o going crazy and mounting the Memory Controller onto the DIMM.

The Serial Connection to the CPU would be standardized and use the OMI interface, ergo saving plenty of die area on the cIOD for AMD and easily opening up many of the pins on the CPU Socket for more PCIe lanes and not needing to save so many pins for DIMM slots.

By: Kamen Rider Blade

Kamen Rider Blade — Thu, 20 Apr 2023 00:47:47 +0000

We need double-height DIMMs to start becoming standard in the server world.

By: Lasertoe

Lasertoe — Tue, 11 Apr 2023 20:43:02 +0000

I see you doing a lot of DRAM capacity/core math but 24 DIMMs per socket seems to be more for applications like large databases (e.g. SAP HANA)where DRAM capacity is often more important than direct DRAM bandwidth.

Having slower 2DPC bandwidth would still be faster than going through additional sockets (when you have to go from 1 to 2 or from 2 to 4 sockets just because of capacity). There is also a latency penalty with additional sockets.

@Yuno

MCR will not have a lot of difference from LR DIMMs when it comes to signal strength.

By: Yuno

Yuno — Mon, 10 Apr 2023 05:23:44 +0000

Why isn’t MCR mentioned in this article at all? It seems to solve more or less the same issues with less memory traces on the motherboard

By: Chris S

Chris S — Sun, 09 Apr 2023 07:57:16 +0000

@Benny_rt2

Those cards have expander chips that add latency and reduce bandwidth (and also add cost) so they are only used where memory capacity outweighs all other concerns.

@TS

SODIMM and CAMM don’t solve the problem. The problem is that there are only so many memory chips you can put on a DIMM – usually 32 for RDIMMs. SODIMMs have a max of 16 memory chips, so even though they take up half the space, they also have half the capacity. CAMM also has limited area for memory chips because of its horizontal orientation.

3DS memory is the primary way to meet high capacity with 1DPC but it also costs exponentially more as you point out.

The 2DPC market is mainly there for people who want to save money by using more of the cheaper, lower density DIMMs and are willing to tradeoff bandwidth for the cost savings.