Comments on: Marvell Custom HBM Compute Architecture for Custom Hyper-Scale XPUs https://www.servethehome.com/marvell-custom-hbm-compute-architecture-for-custom-hyper-scale-xpus/ Server and Workstation Reviews Wed, 11 Dec 2024 16:16:51 +0000 hourly 1 https://wordpress.org/?v=6.7.1 By: fuzzyfuzzyfungus https://www.servethehome.com/marvell-custom-hbm-compute-architecture-for-custom-hyper-scale-xpus/#comment-594744 Wed, 11 Dec 2024 16:16:51 +0000 https://www.servethehome.com/?p=82647#comment-594744 If I’m understanding this correctly it looks like they are going with a high speed serial interface rather than a broad parallel one(as seems to be periodically tried in RAM, whether with totally different RAM types like what RAMBUS did, or tack-ons like with FB-DIMM).

Do we know whether this arrangement requires a totally different flavor of HBM built from the ground up to suit the serial interface; or is it more FB-DIMM like in being ‘normal’ HBM but having some sort of translator at the bottom of the stack that implements the serial interface (like the ABM on an FB-DIMM which handled abstracting the normal DDR into a serial interface back to the memory controller)?

Also, since this seems to be a thing with let’s-make-memory-serial-because-fast-wide-multidrop-busses-kind-of-suck; are there expected to be latency implications?

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